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Technical Lead Digital Design Engineer

Astera Labs

$160,000 / year

San Jose, California, United StatesFull-timeOn-siteProficient

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Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Overview  
Join our team as Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.  

Key Responsibilities  

  • Own the RTL implementation of complex digital designs from micro-architecture through sign-off.  
  • Collaborate with verification teams to review test plans and debug issues.  
  • Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.  
  • Scripting and automation for ASIC methodology improvement.  
  • Accountable for quality and overall design success with the support of senior engineers.  

Required Qualifications  
Education & Experience:  

  • Bachelor’s degree in electrical engineering or equivalent  
  • 5+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets  

Digital Design Expertise:  

  • Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.  
  • Track record of delivering high-quality digital designs from definition to production.  
  • Experience in high-speed design in advanced technology nodes.  
  • Understanding of functional and formal verification at block and chip level.   
  • Understanding of clocking, CDC and RDC and static-timing analysis 

Protocols & Integration:  

  • Proficient with high-speed protocols such as PCIe, Ethernet, DDR, or similar 
  • Experience with IP development and integration  

Tools & Methodologies:  

  • Expertise in design methodology, CAD automation or design infrastructure. 
  • Proven SystemVerilog and Python expertise in a production environment  
  • Familiarity with Synopsys and/or Cadence digital design flows  
  • Basic understanding of UVM-based verification methodologies  

Professional Attributes:  

  • Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment  
  • Good communication and collaboration skills; comfortable working cross-functionally with global teams  
  • Self-directed learner who adapts quickly to changing requirements  
  • Customer-focused mindset with the ability to prioritize and work independently to deliver high-quality designs.  

Preferred Qualifications  

  • Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus  
  • Knowledge of design-for-test (DFT) in a production environment. 

Base salary range is $160,000 USD-$200,000 USD,and will be determined based on the candidate's capabilities and employees in similar positions.  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About this role

Astera Labs is seeking a Technical Lead Digital Design Engineer to own RTL implementation for complex digital blocks across their high-performance connectivity platform. You'll drive designs from micro-architecture through silicon bring-up, working across verification, physical design, and test teams to deliver production-quality silicon in advanced technology nodes. This role requires you to balance technical depth with leadership—you'll be accountable for design success while collaborating with senior engineers and cross-functional teams globally.

The position demands five or more years shipping SoC and silicon products in server, storage, or networking environments, with strong expertise in SystemVerilog RTL coding, synthesis flows (Synopsys or Cadence), and high-speed protocols like PCIe and Ethernet. You'll need solid grounding in timing closure, design-for-test implementation, formal verification, and clocking/CDC concepts. Scripting and automation skills in Python and CAD tools are expected to improve ASIC methodology. Experience with IP development, embedded processors, or production DFT is valued but not required.

This is an in-office role in San Jose with a base salary of $160,000 to $200,000, depending on your background and experience level.

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Pay for this role

$160,000 per year

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