Principal Physical Design CAD Engineer
Astera Labs
Salary undisclosed
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Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies.
This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.
Key Responsibilities
The Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.
Key responsibilities include:
- Develop and support physical design CAD flows using industry-standard EDA tools
- Build automation infrastructure for implementation, analysis, reporting, and debug
- Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification
- Create scripts and utilities to improve productivity, quality of results, and flow robustness
- Support and enhance flows based on Synopsys Fusion Compiler
- Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity
- Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues
Basic Qualifications
- At least 3 years of experience in Physical Design, CAD, or implementation methodology
- Strong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification
- Hands-on experience with Synopsys Fusion Compiler
- Experience with scripting languages such as Tcl, Python
- Ability to develop automation around EDA tools and large-scale design flows
- Good understanding of timing, power, congestion, floorplanning, and QoR analysis
- Strong debugging and problem-solving skills
- Ability to work closely with multiple engineering teams and support complex design environments
- High motivation to learn and apply GenAI technologies in semiconductor design flows.
Preferred Experience
- Experience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar
- Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows
- Experience building dashboards, regression systems, flow checkers, or automated report analyzers
- Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools
- Experience with Git, CI/CD, databases, or cloud-based compute environments
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About this role
Astera Labs is building a new R&D center in Israel focused on semiconductor design for AI infrastructure, and this role offers the chance to establish physical design CAD practices from the ground up. You would own the parasitic extraction methodologies and flows that ensure high-speed chip designs are modeled accurately through the entire implementation process, from RTL to GDSII. This is a foundational position where your work directly impacts how the team approaches synthesis, placement, routing, timing closure, and signoff across complex connectivity chips.
The day-to-day involves developing and maintaining CAD automation around industry-standard EDA tools—primarily Synopsys Fusion Compiler—while supporting design teams across multiple implementation stages. You'll write scripts in Tcl and Python to improve productivity and flow robustness, analyze tool outputs and QoR metrics to identify bottlenecks, and troubleshoot timing, power, and physical verification issues. A significant part of the role is exploring how GenAI can accelerate debugging, automate repetitive work, and enhance reporting within semiconductor design flows.
You should have at least three years of hands-on experience in physical design or implementation methodology, with solid grounding in digital design concepts and timing closure. Strong scripting skills and the ability to build automation around EDA tools are essential. Experience with additional tools like PrimeTime, StarRC, or Calibre, familiarity with STA and low-power design, and exposure to GenAI or LLM-based tools would strengthen your candidacy, though the role emphasizes motivation to learn and apply these emerging methodologies.
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Astera Labs stock may move 11% on Nov. 3 earnings report, Investing.com
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