Staff/ Principal Chip Top Physical Design Engineer
Astera Labs
Salary undisclosed
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Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.
As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.
Key Responsibilities
- Execute SoC Top-level physical design and actively drive full-chip convergence
- Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
- Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
- Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
- Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration
Basic Qualifications
- B.Sc. or M.Sc. in Electrical Engineering
- 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
- Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills
- Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
- Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
- Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration
Preferred Qualifications
- Deep understanding of Power & Noise analysis (EM/IR)
- Experience with DFT (Design for Test) integration into the physical design flow
- Background in high-speed interfaces or data center protocols
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About this role
Astera Labs is building an R&D center in Israel focused on semiconductor design for AI infrastructure, and this role sits at the center of that effort. You would own the physical design and implementation of system-on-chip (SoC) top-level designs for high-performance connectivity chips deployed in the world's largest AI clusters. This means driving the full journey from floor-planning through tape-out—executing place and route, clock tree synthesis, power distribution, and all signoff criteria (timing, power integrity, DRC, LVS, and more) to meet extreme performance, power, and area targets.
The work demands deep hands-on expertise across the RTL-to-GDS flow and mastery of tools like Synopsys ICC2 or Cadence Innovus. You'll collaborate with architecture, design, DFT, and product teams to solve complex signal integrity and thermal challenges in advanced process nodes (5nm and below), and partner with the package team on design details like bump mapping. This is a role for someone with at least five years of chip-level physical design experience at a leading semiconductor company who can navigate complexity, communicate clearly across teams, and drive projects to convergence.
If you've spent years in backend design on cutting-edge processes and want to work on infrastructure that directly enables AI at scale, this is a hands-on technical leadership opportunity in a newly formed center where your impact will be visible from day one.
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Astera Labs stock may move 11% on Nov. 3 earnings report, Investing.com
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