Principal Verification Engineer
Astera Labs
$185,000 - $230,000 / year
Need a reasonable accommodation to apply or interview? Contact us.
JobMinglr uses automated technology to recommend jobs based on profile information and job preferences. Match Score does not determine eligibility for a position, prevent a user from viewing or applying to a job, or make hiring decisions on behalf of an employer.
Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.
Key Responsibilities
- Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
- Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
- Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
- Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
- Work with RTL designers to troubleshoot and resolve design issues.
- Drive verification strategy and methodology for SoCs in server and networking applications.
Required Qualifications
- Bachelor’s degree in Electrical Engineering (Master’s preferred).
- 8+ years of experience in SoC verification, particularly for server and networking applications.
- Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
- Proficiency with industry-standard simulators, version control, and regression systems.
- Strong debugging and coverage analysis skills.
- Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
- Familiarity with verification of switching architectures, including packet processing and forwarding engines.
- Excellent communication skills and ability to work independently with minimal supervision.
Preferred Qualifications
- Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
- Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
- Knowledge of Ethernet/PCIe switching and central buffer architectures.
- Experience with emulation platforms and hardware-software co-verification
Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Benefits
- bonus
About this role
Astera Labs is building the connectivity infrastructure that powers AI at scale, and this Principal Design Verification Engineer role sits at the center of that mission. You'd own the full verification lifecycle for complex ASICs used in server and networking applications—from test planning and development through debugging and coverage closure. The work demands deep expertise in SystemVerilog/UVM and the ability to apply both directed and constrained-random verification techniques, alongside collaboration with RTL designers, software teams, and system validation engineers to catch design issues before they reach production.
This is a senior-level position suited to someone with 8+ years of SoC verification experience, ideally with hands-on familiarity with switching architectures, packet processing, and the verification tools that support emulation and regression testing. You'll need strong debugging instincts, the ability to analyze coverage gaps methodically, and proficiency in scripting languages like Python or C/C++. Experience with protocol verification IPs (PCIe, Ethernet, InfiniBand) and NoC architectures is valued but not required; what matters most is a track record of driving verification strategy and the independence to own complex problems.
The role is based in San Jose and requires in-office presence. Compensation ranges from $185,000 to $230,000 depending on experience, with eligibility for bonus and benefits.
How this employer is doing
average
- H1B: Sponsors Visas
- Sponsors Visas
This role's local market on JobMinglr
Pay for this role
$185,000 to $230,000 per year
That is the employer's posted range, and where you land in it is usually decided in one conversation. Before that conversation, run the numbers: analyze an offer for this role.
Before you apply, worth reading
How JobMinglr reads this job
Every listing here is scored against your profile before you apply: skills overlap, experience level, location and work arrangement, each weighted and explained. You see the score and the reasons, not just a list. How the matching works.