Sr. IC Package Design Engineer (Silicon Engineering)
Spacex
Salary undisclosed
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Description
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. IC PACKAGE DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in-house ASICs and RFICs for digital beam formers and modems.
RESPONSIBILITIES:
- Own and drive advanced package selection, new product BGA configuration and package structure
- Responsible for package/SIP layout, optimization, design verification and tapeout
- Interface and coordinate with cross-functional groups throughout SpaceX on new product package selection, feasibility analysis and design
- Work cross-functionally, understand trade-offs, constraints, and optimizing silicon floor plan, bump and package pin out
- Simulate and optimize signal/power integrity and RF performance of the package design
- Drive methodology, innovations, and productivity improvements in package design
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering, or physics
- 5+ years of experience with IC package design
PREFERRED SKILLS AND EXPERIENCE:
- Experience with Co-packaged Optics (CPO)
- Thorough understanding of signal and power integrity fundamentals
- Substrate design experience for RF, digital, high-speed and mixed signal die
- Experience with Cadence APD+/SIP or similar design tools
- Experience in package design electrical review, SI/PI analysis
- Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, ADS
- Experience in package design for manufacturing reviews
- Familiar with BGA package substrate technologies
- Strong problem solving skills with strong engineering fundamentals
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours or weekends as needed to meet mission critical deadlines
ITAR REQUIREMENTS:
- To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.
About this role
SpaceX is building the silicon that powers Starlink's global satellite constellation and ground infrastructure, and this role puts you at the center of that effort. As a Senior IC Package Design Engineer, you'll own the full packaging strategy for custom ASICs and RFICs—from initial selection and BGA configuration through layout, simulation, and tapeout. You'll work directly with systems, firmware, and ASIC teams to optimize signal and power integrity, RF performance, and manufacturability while balancing competing constraints across silicon floor plan, bump configuration, and pin assignment.
This position demands deep expertise in IC packaging fundamentals and hands-on proficiency with industry tools like Cadence APD+/SIP, SIWave, HFSS, and ADS. You should bring at least five years of package design experience, ideally including substrate design for RF and high-speed mixed-signal applications, and a track record of driving methodology improvements and design innovation. The role also values problem-solving ability and strong engineering fundamentals across signal and power integrity.
Based in Austin and required to work in-office, this is a full-time position that may demand extended hours to meet mission-critical deadlines. U.S. citizenship or equivalent ITAR authorization is required.
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