Staff Digital Verification Engineer
Onsemi
Salary undisclosed
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Description
Key Responsibilities
- Expected to take ownership and lead verification efforts across IP, subsystem, and SoC-level projects and work independently.
- Independently Architect and develop reusable verification environments using System Verilog and UVM.
- Create constrained-random, directed, and scenario-based test cases.
- Develop scoreboards, monitors, protocol checkers, assertions (SVA), and coverage models.
- Analyze and debug RTL and gate-level simulation failures for timing and functional signoff.
- Analyze, debug, and enhance C/C++ golden reference models for functional verification.
- Execute, and debug fault injection simulations to validate functional safety requirements and fault handling mechanisms.
- Collaborate closely with design, DFT, physical design, and architecture teams to resolve issues and support sign-off activities.
Work with AI-assisted engineering tools (e.g., GitHub Copilot, Microsoft Copilot, LLM-based code generation/debug tools, AI-driven verification productivity solutions) to enhance regression infrastructure and verification automation
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Qualifications
- Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
- 6-10 years of hands-on experience in Digital/ASIC/SoC Verification.
- Strong expertise in: System Verilog (Mandatory) and UVM (Mandatory)
- Familiarity with industry-standard simulators such as Xcelium and Questa.
- Verification experience with some or all protocols such I2C, AHB/APB, MIPI
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More details about our company benefits can be found here:
About this role
Onsemi is seeking a Staff Digital Verification Engineer to lead verification efforts across multiple levels of complexity—from individual IP blocks through full SoC designs. You would own the architecture and development of reusable verification environments using SystemVerilog and UVM, creating constrained-random and scenario-based test cases while building the supporting infrastructure of scoreboards, monitors, protocol checkers, and coverage models. The role also involves debugging RTL and gate-level failures, enhancing C/C++ golden reference models, and executing fault injection simulations to validate functional safety requirements.
This position demands 6–10 years of hands-on digital or ASIC verification experience and a master's degree in electronics or a related field. You'll need strong expertise in SystemVerilog and UVM, familiarity with simulators like Xcelium or Questa, and ideally some exposure to protocols such as I2C, AHB/APB, or MIPI. The role is based in Bangalore and requires in-office presence.
Beyond technical depth, you'll collaborate across design, DFT, physical design, and architecture teams to resolve issues and support sign-off activities. The position also emphasizes working with AI-assisted engineering tools to enhance regression infrastructure and verification automation, making it a fit for engineers who want to blend traditional verification rigor with emerging productivity tools.
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Pay for this role
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