Tech Lead, Digital Design Engineer
Astera Labs
$175,500 - $195,000 / year
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Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.
This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams. You will help advance scalable fabric solutions built around UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet as Astera Labs continues to deliver purpose-built connectivity for demanding AI workloads.
Key Responsibilities
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Digital Architecture and RTL Design
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Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.
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Develop front-end design solutions for high-performance networking and server connectivity applications.
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Integrate and configure reusable IP while ensuring clean interfaces, performance, and maintainability.
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Design Implementation and Signoff
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Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.
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Analyze design tradeoffs across performance, power, area, and schedule, and resolve implementation issues with cross-functional partners.
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Apply Synopsys and/or Cadence digital design flows to deliver production-quality silicon.
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Verification, Bring-Up, and Technical Leadership
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Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.
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Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues.
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Provide technical leadership, prioritize multiple workstreams, and communicate risks and progress clearly to stakeholders.
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Basic Qualifications
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Bachelor’s degree in Electrical Engineering or a related field.
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5–8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
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Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.
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Proven front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT.
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Experience owning blocks from architecture through GDS and working with Synopsys and/or Cadence design tools and flows.
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Authorized to work in the United States.
Preferred Qualifications
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Master’s degree in Electrical Engineering or a related field.
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Experience developing or supporting PCIe or Ethernet switch products.
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Familiarity with UVM-based design verification and coverage-driven debug.
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Silicon bring-up and debug experience in small-geometry CMOS technologies at 28nm or below.
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Scripting experience with Python or comparable programming languages, along with a collaborative, customer-focused approach.
Salary range is $175,500 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Benefits
- bonus
About this role
Astera Labs is building the connectivity backbone for AI infrastructure, and this Tech Lead role puts you at the center of that mission. You'd own the front-end digital design of high-performance switch ASICs, translating microarchitecture into production RTL and driving block-level execution from synthesis through physical implementation. The work spans UALink, PCIe Gen 6/7, Ethernet, and other cutting-edge protocols—technologies that directly enable the hyperscale AI systems reshaping the industry.
This is a leadership position that demands both deep technical hands-on skills and the ability to coordinate across verification, physical design, and systems teams. You'll need 5–8 years shipping complex SoCs or switch ASICs, proven expertise in high-speed protocol design, and fluency with Synopsys or Cadence flows. The role also expects you to support silicon bring-up and debug, partner on verification strategy, and communicate technical risk clearly to stakeholders. If you've owned blocks end-to-end and thrive in high-performance connectivity or networking silicon, this aligns well. The position is full-time, in-office in San Jose, with a salary range of $175,500–$195,000.
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Pay for this role
$175,500 to $195,000 per year
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