AE| Principal Product Application Engineer (Scorpio)
Astera Labs
Salary undisclosed
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Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description:
As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to ODMs to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. We need experience supporting the development and designing-in of semiconductor products for PCIe/CXL. There are opportunities to support key ODMs directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.
Basic Qualifications
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred.
- Minimum of 10 years’ experience designing in complex SoC/silicon products with a high speed (preferably PCIe) interface.
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
Required Experience
- Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 4.0 at a minimum, some experience with 5.0/CXL preferred.
- Silicon/System bring-up and debug experience in customer systems.
- Technical ownership of issue resolution: Driving and directing internal teams, and driving communication to customers through FAE and sales teams.
- Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.
- Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences.
- Global customer engagement support, with travel as required for on-site activities, reviews, and system bring-up.
Preferred experience
- Triaging complex customer reported issues which require taking into account multiple layers of conditions; for instance, silicon, firmware, hardware board design, and system environment.
- Development/support for PCIe or Ethernet Switch or Retimer products.
- PCIe compliance testing methodology and troubleshooting.
- Comfort working with software/firmware associated with semiconductor products, such as; Firmware development with C-language, scripting with Python or other equivalent programming languages.
- Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About this role
Astera Labs is seeking a Principal Product Application Engineer to serve as a technical bridge between the company's PCIe and CXL connectivity solutions and the ODMs designing them in. You'll provide hands-on guidance to customers navigating complex design challenges, generate technical documentation and application notes, and feed product insights back to internal teams. This role blends field support with lab work—you'll travel to customer sites for system bring-up and debug, then return to the bench with protocol analyzers and high-speed oscilloscopes to troubleshoot leading-edge semiconductor integration issues.
The position requires at least 10 years of hands-on experience designing high-speed silicon products into systems, with deep expertise in PCIe physical layer standards and debug (PCIe 4.0 minimum, ideally with 5.0 or CXL exposure). You'll own issue resolution end-to-end, directing internal teams and driving customer communication through FAE and sales channels. Strong technical writing skills are essential for creating clear internal and customer-facing guides. A Bachelor's degree in electrical engineering is required; a Master's is preferred.
This role suits someone comfortable wearing multiple hats—part field engineer, part systems troubleshooter, part technical writer—with the entrepreneurial mindset to drive solutions in a fast-moving AI infrastructure space. Experience with data center systems, PCIe compliance testing, or firmware development would strengthen your candidacy. The position is based in San Jose and requires in-office presence.
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