Tech Lead, Digital Design Engineer
Astera Labs
Salary undisclosed
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Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description
We are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.
Basic Qualifications:
- Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
- +3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately.
Required Experience:
- Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
- Proven front end design skill – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
- Block level ownership from architecture to GDS.
- Experience with Synopsys and/or Cadence digital design tools/flows
- Knowledge of design for test (DFT)
- Familiarity with UVM based design verification
- Silicon bring-up and debug experience
- Small-geometry CMOS (≤28nm) design
Preferred Experience:
- Scripting with Python or other equivalent programming languages.
- Development/support for PCIe or Ethernet Switch products.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About this role
Astera Labs is seeking a Tech Lead, Digital Design Engineer to drive front-end circuit design for high-performance network controllers that power AI infrastructure. You would own block-level design from architecture through GDS, working with advanced protocols like PCIe, ULink, and Ethernet. This role demands hands-on expertise across the full digital design flow—RTL development, synthesis, timing closure, verification, and silicon bring-up—along with proficiency in industry-standard tools from Synopsys and Cadence.
The ideal candidate brings at least three years of experience developing complex SoCs for networking, switching, or server applications, with demonstrated strength in high-speed protocol design and small-geometry CMOS (28nm and below). You should be comfortable with design-for-test methodologies, UVM-based verification, and silicon debug. This is an in-office role in San Jose requiring immediate availability and US work authorization.
If you have a strong EE foundation (Bachelor's required, Master's preferred), thrive working independently on dynamic priorities, and bring a customer-focused mindset to a fast-moving environment, this position offers the chance to shape connectivity solutions at scale for the AI era.
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