Staff Digital Verification Engineer
Onsemi
Salary undisclosed
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Description
- Verify digital top-level subsystem IP within the TREO platform, ensuring robust functionality and performance across use cases.
- Develop and execute constrained random verification environments using SystemVerilog and UVM.
- Architect and implement testbenches, including:
- Scoreboards
- Monitors
- Stimulus generators
- Checkers
- Define and track functional and code coverage, driving closure against defined verification plans.
- Perform and integrate formal verification techniques where applicable.
- Debug complex system-level issues across digital and mixed-signal boundaries.
- Collaborate closely with:
- Digital design teams
- Analog/mixed-signal design teams
- System architects
- Contribute to verification strategy and methodology improvements, including reuse and scalability.
- Utilize tools such as Questa (Mentor/Siemens) for simulation and debugging.
Qualifications
- Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering, or related discipline.
- 5+ years of industry experience in digital verification.
- Strong hands-on experience in:
- SystemVerilog and UVM
- Constrained random verification methodologies
- Formal verification techniques
- Solid understanding of digital design fundamentals (RTL design, timing, interfaces, etc.).
- Proven experience in:
- Testbench architecture and development
- Scoreboards, monitors, and checkers
- Functional and code coverage methodologies
- Experience with Questa or equivalent simulation tools.
- Demonstrated ability to work across digital and analog/mixed-signal interfaces.
- Experience working on automotive or high-reliability semiconductor products.
- Familiarity with mixed-signal verification challenges.
- Exposure to AI-enabled verification flows, such as:
- Coverage acceleration
- Intelligent stimulus generation
- Debug automation
- Knowledge of modern verification flows for large subsystem or SoC-level designs.
- Familiarity with scripting (Python, Tcl, or similar) for automation.
Key Skills
- Strong analytical and debug capabilities.
- Ability to work effectively in cross-functional teams.
- Clear communication skills (technical and non-technical).
- Proactive mindset with a focus on quality and continuous improvement.
More details about our company benefits can be found here:
About this role
Onsemi's Cork facility is seeking a Staff Digital Verification Engineer to own verification of digital subsystems within the TREO platform. You'll architect and execute constrained random verification environments using SystemVerilog and UVM, develop comprehensive testbenches with scoreboards and monitors, and drive functional and code coverage closure. The role spans simulation, formal verification, and debug of complex issues at digital and mixed-signal boundaries, requiring close collaboration with design teams across disciplines.
This position demands at least five years of hands-on verification experience, with proven expertise in SystemVerilog, UVM, constrained random methodologies, and formal verification techniques. You'll need solid grounding in digital design fundamentals and demonstrated success building testbench architectures and coverage strategies. Proficiency with Questa and the ability to work across analog and digital interfaces are essential; scripting skills and familiarity with modern SoC-level verification flows are valued additions.
The role suits someone with strong analytical and debug capabilities who thrives in cross-functional environments and takes a proactive approach to quality. Experience in automotive or high-reliability semiconductor products, mixed-signal verification challenges, or AI-enabled verification flows would strengthen your candidacy. This is a full-time, in-office position in Cork.
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Pay for this role
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