Staff Digital Design Engineer
Onsemi
Salary undisclosed
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Description
Key Responsibilities
- Architect, design, and implement digital FSM-based controllers that manage and interact with analog power, clocking, and mixed-signal blocks
- Deliver robust digital-on-top subsystem IP in support of the onsemi Treo™ platform
- Develop clean, maintainable RTL (SystemVerilog / Verilog) suitable for reuse and scalability
- Collaborate closely with:
- Analog and mixed-signal designers to define control interfaces and behavior
- Verification engineers to ensure functional correctness
- Physical design teams to support timing, power, and area goals
- Contribute to digital verification activities, including:
- Testbench development
- Block-level and subsystem-level verification
- Debug and root-cause analysis
- Support digital back-end flows, including synthesis, timing closure, and low-power considerations
- Mentor junior engineers and contribute to best practices within the Core Platform IP team
- Stay technically curious and engaged, particularly around emerging AI-assisted methodologies for digital design and verification
Qualifications
Required Qualifications
- 5+ years of relevant experience in digital IC design
- Strong hands-on experience with digital RTL design, including FSM-based control logic
- Proven experience designing digital logic that interfaces with analog power and clocking systems
- Solid understanding of digital design fundamentals:
- Clock-domain crossing (CDC)
- Reset strategies
- Low-power techniques
- Timing constraints
- Experience with digital verification, including simulation-based verification
- Exposure to digital back-end flows, such as synthesis, STA, and handoff to physical design
- Strong problem-solving skills and a system-level mindset
- Excellent communication skills and ability to work in a cross-functional environment
Preferred / Nice-to-Have Qualifications
- Experience delivering reusable IP or platform-level subsystems
- Familiarity with UVM-based verification environments
- Experience in mixed-signal or power management ICs
- Knowledge of low-power standards (e.g., UPF/CPF)
- Interest in or early adoption of AI/ML tools applied to digital design, verification, or productivity workflows
More details about our company benefits can be found here:
About this role
Onsemi is seeking a Staff Digital Design Engineer to architect and implement digital controllers for the Treo platform, focusing on FSM-based logic that manages interactions between digital, analog, power, and mixed-signal subsystems. You'll own the full design lifecycle—from RTL development in SystemVerilog through verification, synthesis, and timing closure—while collaborating with analog designers, verification engineers, and physical design teams to deliver reusable, scalable IP. The role demands deep expertise in digital fundamentals like clock-domain crossing, reset strategies, and low-power techniques, plus hands-on experience shipping mixed-signal or power management ICs.
This is a senior individual contributor and mentoring role based in Cork, requiring at least five years of digital IC design experience and a proven track record with control logic and analog-interfacing blocks. Beyond core competencies in RTL design and simulation-based verification, you should bring system-level thinking, strong cross-functional communication, and ideally exposure to UVM verification frameworks, low-power standards, or emerging AI-assisted design tools. The position suits engineers who thrive on technical depth, enjoy solving complex integration challenges, and want to shape design practices within a platform IP team at a company focused on automotive, industrial, and energy applications.
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Pay for this role
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