Tech Lead PCB Layout Engineer
Astera Labs
Salary not disclosed
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Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
At Astera Labs, we seek a motivated and experienced Tech Lead PCB Layout Engineer to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will design complicated PCB layout across multiple fields including high-speed interfaces, power, high-density interconnect, etc. This position will be onsite.
Basic Qualifications
- Strong academic/technical background in electrical engineering or similar degree; Bachelor’s is required;
- 10+ years of experience designing top-tier complex PCB (40,000+ pins, 30+ layer count) across high-speed differential pairs, RF, high-power, high-density interconnect (HDI), etc.
- Capable of full PCB design process from feasibility study, to DFM and Gerber release.
- Have a proven track record with achieving layout design for signal integrity, power integrity, DFT, and DFM.
- Cross-functional design mentality with the electrical design community to develop systems.
- Self-starting, professional, and hands-on work ethic that can execute intense design work in a dynamic environment.
- Proven track record solving problems independently, preferably as a tech lead.
- Prefer previous work experience with oversee customers and proficient in speaking/written English.
Required Experience
- Proficient in PCB designs with PCIe Gen5/6, Ethernet 112G/224G PAM4, and DDR4/5 applications.
- Proficient in advanced PCB technologies such as micro-vias, blind vias, any layer HDI, back-drilling, and sequential lamination, step gold finger, etc.
- Master EDA tools including Cadence Allegro, Polar SI9000, CAM350 or similar DFM inspection tools, and AutoCAD.
- Proficient in PCB design rules, constraint manager, checklist, etc.
- Possess decent speaking and written English skills.
- Familiar with PCB manufacture and PCB assembly process and capable of handling PCB/PCBA EQ.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About this role
Astera Labs is looking for a seasoned PCB layout engineer to lead design efforts on high-speed connectivity solutions built for AI infrastructure. You would own complex multilayer boards (30+ layers, 40,000+ pins) spanning high-speed interfaces, power delivery, and dense interconnects—working across PCIe Gen5/6, Ethernet 112G/224G PAM4, and DDR4/5 technologies. The role demands hands-on execution from feasibility through DFM and Gerber release, with particular focus on signal integrity, power integrity, and manufacturability.
This is a tech lead position, so you'll need a track record of independent problem-solving and ideally prior leadership experience. You should be fluent in Cadence Allegro, Polar SI9000, and CAM350, comfortable with advanced manufacturing techniques like micro-vias and sequential lamination, and able to navigate the full PCB and PCBA process. A minimum of 10 years designing top-tier complex boards is required, along with a bachelor's degree in electrical engineering or equivalent. The role is based in Shanghai and requires in-office presence, with proficiency in spoken and written English essential for cross-functional collaboration with design teams and customer engagement.
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