Principal Logic Design Engineer - UALink IP/Subsystem
Astera Labs
Salary not disclosed
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Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Logic Design Engineer – UALink IP/Subsystem
Experience
10–15 years
Job Summary
We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems.
Key Responsibilities
- Lead architecture and RTL development for UALink IP/subsystems.
- Translate protocol and system requirements into scalable hardware architecture.
- Design high-bandwidth, low-latency data paths and control logic.
- Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
- Define interfaces between UALink and other SoC/interconnect components.
- Develop and review SystemVerilog RTL.
- Drive design optimization for performance, power, area, and latency.
- Work closely with verification, physical design, SoC integration, and firmware teams.
- Review design specifications and contribute to architectural decisions.
- Debug complex simulation and integration issues.
- Provide technical leadership and mentorship.
Required Skills
- Strong experience in RTL and microarchitecture development.
- Experience with high-speed interconnects and/or coherent fabrics.
- Strong understanding of computer architecture, networking/interconnect concepts, and data movement.
- Proficiency in SystemVerilog/Verilog.
- Strong understanding of CDC, reset architecture, performance, and hardware design methodology.
Preferred
- Direct UALink experience.
- Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.
- Experience in AI/accelerator or high-performance compute systems.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About this role
Astera Labs is seeking a Principal Logic Design Engineer to lead the architectural and RTL development of UALink-based IP and subsystems—a critical component of their rack-scale AI infrastructure platform. This role demands 10–15 years of experience in high-performance interconnect and SoC design, with the ability to translate complex protocol and system requirements into scalable hardware architectures. You would own the design of high-bandwidth, low-latency data paths, flow control, buffering, arbitration, and error-handling mechanisms, while driving optimization across performance, power, area, and latency.
The position requires deep expertise in RTL and microarchitecture development using SystemVerilog, combined with solid knowledge of computer architecture, networking concepts, and data movement principles. Hands-on experience with high-speed interconnects, coherent fabrics, CDC, and reset architecture is essential. Prior exposure to UALink, PCIe, CXL, CCIX, CHI, or Ethernet protocols, or work in AI accelerators and high-performance compute systems, would be valuable.
You would work closely with verification, physical design, SoC integration, and firmware teams, taking on technical leadership and mentorship responsibilities while debugging complex simulation and integration challenges. This is an in-office, full-time role based in Bengaluru.
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