Lead Logic Design Engineer
Astera Labs
Salary not disclosed
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Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Lead Logic Design Engineer
Experience
6-10 years
Job Summary
We are seeking a Lead Logic Design Engineer with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up.
Key Responsibilities
- Lead RTL/microarchitecture development for complex connectivity IP/subsystems.
- Translate specifications and system requirements into robust hardware architecture.
- Design high-performance and scalable logic for controllers/subsystems.
- Work across connectivity IP / subsystem layers including Transaction, Data Link, and Physical interface integration as applicable to the role.
- Develop and review RTL using SystemVerilog/Verilog.
- Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
- Drive performance, latency, area, and power optimization.
- Collaborate with verification teams to develop verification strategies and debug complex failures.
- Work with SoC integration and physical design teams to ensure successful implementation.
- Lead technical reviews and mentor senior engineers.
- Support post-silicon debug and root-cause analysis.
Required Skills
- Extensive experience in complex connectivity IPs such as PCIE, UALink, Ethernet, CXL, UCIe.
- Strong RTL design experience using SystemVerilog/Verilog.
- Deep knowledge of PCIe architecture and protocol.
- Strong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling.
- Experience with simulation, lint, CDC, synthesis, and timing considerations.
- Strong debugging and problem-solving skills.
Preferred
- Experience of working in switching silicon.
- Experience of working on entire cycle from concept to silicon production.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About this role
Astera Labs is looking for a Lead Logic Design Engineer to own the architecture and RTL implementation of complex connectivity IP subsystems that form the backbone of their AI infrastructure platform. This role requires someone with 6–10 years of experience in microarchitecture and RTL design who can translate system requirements into high-performance hardware, working across protocol layers like PCIe, CXL, Ethernet, and UALink. You'll be responsible for the full technical journey—from specification through silicon bring-up—designing robust logic for controllers, optimizing for performance and power, and collaborating with verification, integration, and physical design teams to bring designs to production.
The ideal candidate has deep expertise in connectivity protocols (particularly PCIe), strong SystemVerilog/Verilog skills, and hands-on experience with simulation, synthesis, timing analysis, and post-silicon debug. You'll need to demonstrate proficiency in designing high-speed data paths, flow control mechanisms, arbitration, and error handling. Beyond technical depth, this is a leadership position—you'll mentor senior engineers, lead technical reviews, and drive complex problem-solving across teams. Experience spanning the full concept-to-production cycle and familiarity with switching silicon are valued additions.
This is an in-office, full-time role based in Bengaluru. It suits engineers who thrive on technical ownership of mission-critical IP in a fast-moving AI infrastructure company and who are ready to step into a leadership capacity within the design function.
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Should Investors Hold on to Astera Labs Stock Post Q2 Earnings?, Yahoo Finance
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