Hardware Engineer (FPGA)
Virtu Financial
Salary undisclosed
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Description
Virtu is a leading financial firm that leverages cutting edge technology to deliver liquidity to the global markets and innovative, transparent trading solutions to our clients. As a market maker, Virtu provides deep liquidity that helps to create more efficient markets around the world. Our market structure expertise, broad diversification, and execution technology enables us to provide competitive bids and offers in over 19,000 securities, at over 235 venues, in 36 countries worldwide.
THE ROLE
Virtu's Hardware Design team builds the FPGA and ASIC applications at the core of the firm's proprietary low-latency trading platform.
We are looking for an FPGA/ASIC Engineer to join us. The ideal candidate will be a creative and ambitious hardware engineer who is excited to work on our low-latency trading infrastructure. You'll work on challenging problems alongside a small, international team.
In this role you will:
- Design and develop RTL for new low-latency trading applications
- Own designs end to end, from specification through verification to production deployment
- Improve the team's build, simulation, and verification infrastructure
- Coordinate and execute hardware deployments in live production environments
Virtu offers a dynamic, meritocratic environment with a flat hierarchy. No finance background is necessary or expected. This is a great opportunity for the right candidate to start a career in the financial technology space.
THE CANDIDATE
- Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or a related field
- 2+ years of professional FPGA or ASIC experience (an advanced degree may substitute)
- Strong RTL design and verification skills (SystemVerilog/VHDL, cocotb)
- Familiarity with FPGA/IC design flows and vendor toolchains (Xilinx/AMD, Synopsys, Cadence)
- Working knowledge of high-speed interfaces (Ethernet/MAC/PHY, PCIe, AXI)
DESIRED BUT NOT REQUIRED
- Programming in Python, C++, or similar
- Back-end physical design experience
- Understanding of network protocols and packet processing (TCP/UDP, IP multicast, and hardware protocol offloading)
BENEFITS
- Generous Time Off: 26 days annual leave, plus additional leave for community service, marriage/civil partnerships, and moving house
- Family Support: Paid maternity leave and enhanced paternity leave
- Comprehensive Health & Wellbeing: Private health, dental, and optical cover, GP access, and a dedicated wellness programme
- Financial Protection: Life assurance, income protection, and a competitive pension scheme
- Active Lifestyle Perks: Gym subsidy/fitness reimbursement and Cycle to Work scheme
- Commuting Made Easy: Commuter benefit plan
- Travel Cover: Personal travel insurance
- Daily Perks: Complimentary catered lunches every day, laundry service, onsite gym, barber and hairdresser service
Virtu Financial is an equal opportunity employer, committed to a diverse and inclusive workplace, welcoming you for who you are and does not discriminate on the basis of race, national origin, gender, gender identity, sexual orientation, protected veteran status, disability, age, or other legally protected status.
Benefits
- parental leave
- commuter benefits
About this role
Virtu Financial's Hardware Design team is seeking an FPGA/ASIC engineer to develop the low-latency trading infrastructure that powers the firm's global market-making operations. You would design and own RTL implementations end to end—from specification through verification to live production deployment—working on a small, international team tackling genuinely demanding technical problems. The role also involves improving the team's build and simulation infrastructure and coordinating hardware deployments in production environments.
The position requires a bachelor's degree in Electrical Engineering, Computer Engineering, or related field, plus at least two years of professional FPGA or ASIC experience. You'll need strong RTL design and verification skills in SystemVerilog or VHDL, familiarity with standard design flows and vendor toolchains (Xilinx/AMD, Synopsys, Cadence), and working knowledge of high-speed interfaces like Ethernet, PCIe, and AXI. Experience with Python or C++, back-end physical design, or network protocols is valued but not required. No finance background is necessary—Virtu explicitly welcomes engineers new to financial technology.
The Dublin office is in-person, full-time. The company offers substantial benefits including 26 days annual leave, private health and dental cover, gym access, catered lunches, and a competitive pension scheme. The selection process begins with an online HackerRank assessment, followed by a phone screen for advancing candidates.
How this employer is doing
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In the news
Zacks Research Lowers Earnings Estimates for Virtu Financial, MarketBeat
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Pay for this role
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