Director of Buffer & Memory Subsystem Architecture
SK hynix America
CA$250,000 - CA$300,000 / year
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Description
About SK hynix America:
At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.
Work Model: Onsite
Job Title: Director of Buffer & Memory Subsystem Architecture
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite
Job Summary:
As the founding technical lead, this expert will spearhead the HW/SW co-design of next-generation HBF–xPU systems, translating complex AI workload traces into precise architectural policies for caching, prefetching, and data movement. The role demands deep hands-on expertise in memory controllers and performance modeling to define interface contracts and optimize system-level efficiency across the hardware and software stack.
Responsibilities:
- Serve as the founding technical lead of the HBF R&D team, owning HW/SW architecture decisions and technical alignment with headquarters and external partners.
- Lead HW/SW co-design by defining architecture, functional partitioning, and interface contracts across the HBF hardware and software stack.
- Drive HBF system optimization through memory architecture, performance modeling, and system-level implementation.
- Develop HBF system models and event-/trace-driven simulators for AI memory performance analysis.
- Analyze workload performance and optimize latency, bandwidth, and memory efficiency through architecture modeling.
- Validate architectural assumptions and provide data-driven insights for cross-functional architecture decisions.
- Define HBF Memory Architecture and Policies.
Qualifications:
- 8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures, including the development of queueing, scheduling, and buffer management algorithms.
- Strong expertise in system performance analysis, including memory latency, bandwidth, locality, contention, and Workload characterization, with the ability to translate complex workload traces into architectural policies.
- Proven HW/SW co-design experience, including the ability to translate AI workload, compiler, runtime, and inference-engine behavior into memory hierarchy, data-movement, prefetch, scheduling, and programming-model requirements.
- Experience owning system architecture decisions, technical requirements, interface definitions, and performance acceptance criteria across multiple hardware and software components.
- Experience defining functional partitioning and interface contracts across hardware, firmware, drivers, compiler/runtime, and application software.
- Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC, or comparable modeling environments, including event-driven, trace-driven, or queueing-based models.
Benefits:
- Top Tier health insurance at no employee cost
- Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
- 401k Matching
- Flexible Spending Account (FSA) for Health Care & Dependent Care
- Educational reimbursement up to $10,000 per year
- Donation Matching and volunteering opportunities
- Corporate discount programs
- Free Breakfast/Lunch/Dinner provided to employees
Compensation:
Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets. Pay within the provided range varies by work location and may also depend on job-related skills and experience. Your Recruiter can share more about the specific salary range for the job location during the hiring process.
Equal Employment Opportunity:
SK hynix America is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information, or any other status protected under federal, state, or local applicable laws.
In compliance with federal law, SK hynix America also participates in the federal E-Verify program. Upon accepting an offer of employment, all newly hired individuals will be required to complete Form I-9, which includes verifying identity and legal authorization to work in the United States. Please review the official government posters detailing your rights and protections prior to applying:
Benefits
- health insurance
- 401(k)
- paid time off
- parental leave
About this role
SK hynix America is building next-generation AI memory systems, and this role puts you at the center of that effort as the founding technical lead for their HBF–xPU architecture team. You'll own the hardware-software co-design from the ground up, translating AI workload behavior into concrete architectural decisions around caching, prefetching, and data movement. The work spans memory controllers, performance modeling, and system-level optimization—requiring you to move fluidly between hardware specifications, simulation tools, and software requirements while coordinating with headquarters and external partners.
This is a hands-on director role that demands both strategic ownership and deep technical depth. You'll develop simulators and performance models to validate architectural choices, define memory policies and interface contracts across the stack, and drive optimization around latency, bandwidth, and efficiency. The position expects 8+ years of proven experience in memory subsystems, strong capability in workload analysis and HW/SW co-design, and a track record of owning architecture decisions across multiple components. Proficiency with simulation frameworks like Python, C/C++, or SystemC is essential.
The role is based in San Jose and requires full-time, in-office presence. Compensation ranges from $250,000 to $300,000, with comprehensive benefits including fully covered health insurance, educational reimbursement up to $10,000 annually, parental leave, and on-site meals.
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Pay for this role
$250,000 to $300,000 per year
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