System IP RTL Design Lead
Tenstorrent
Salary undisclosed
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Description
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are seeking an experienced and motivated System IP RTL Design Lead to drive the definition and implementation of complex datacenter class IP for our next-generation semiconductor products. The ideal candidate possesses a deep understanding of System IP and SoC architecture, IP integration challenges, and is adept at leading a design team to deliver high-quality, scalable IP solutions. This role requires strong hands-on technical leadership, excellent communication skills, and a proven track record in the successful delivery of silicon IP.
This role is hybrid, based out of Bangalore, India.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A seasoned IP / SoC design leader with 20+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration.
- Skilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs.
- Experienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations.
- A proactive problem solver capable of debugging complex logic across hierarchical levels within pre-silicon simulation, emulation, and post-silicon bring-up environments.
- A collaborative technical leader who can work seamlessly across architecture, design, verification, physical design, software, firmware and external IP vendors.
- Strong communication skills and the ability to mentor and guide engineering teams.
What We Need
- Lead the technical definition, selection, and integration of internally and third party developed IPs including MMUs, Interrupt controllers, Interconnects, Memory controllers, and peripherals within advanced SoCs.
- Define system-level requirements, IP specifications, interfaces, and integration methodologies to achieve performance, power, and area (PPA) goals.
- Drive IP design through sign-off activities while ensuring compliance with functional, security, and quality requirements.
- Bring deep expertise in protocols and interfaces such as AXI/AHB/APB, PCIe, DDR, and USB, along with scripting and verification methodologies including Python, Tcl, UVM, and formal verification.
What You Will Learn
- Work on cutting-edge CPU and AI compute architectures integrating advanced compute, memory, and interconnect technologies.
- Gain exposure to large-scale system integration challenges spanning RTL, verification, physical design, and silicon bring-up.
- Influence key architectural and microarchitectural decisions that directly impact next-generation product performance and scalability.
- Collaborate with highly experienced global engineering teams across multiple domains and disciplines.
- Contribute to the evolution of scalable IP integration methodologies, verification flows, and best practices for future SoC programs.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
About this role
Tenstorrent is building next-generation AI semiconductors around a custom RISC-V architecture, and this role leads the system IP and SoC design efforts that tie together the core compute, memory, and interconnect technologies. You would own the technical definition and integration of complex datacenter-class IP blocks—including MMUs, interrupt controllers, interconnects, memory controllers, and peripherals—while driving them through to silicon sign-off. This is a hands-on leadership position requiring deep expertise in RTL design, high-speed protocols like AXI, PCIe, and DDR, and the ability to make hard PPA trade-offs across a hierarchical design.
The role demands someone with 20+ years of SoC and IP design experience who can lead a team, author specifications, and debug across simulation, emulation, and post-silicon environments. You'll collaborate across architecture, verification, physical design, software, and external vendors—requiring both strong technical judgment and communication skills. Tenstorrent explicitly welcomes candidates at various experience levels and will calibrate the offer accordingly during the interview process.
This is a hybrid position based in Bangalore. Note that employment is contingent on eligibility to access U.S. export-controlled technology, and citizenship or permanent residency status may affect your candidacy due to export compliance requirements.
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