Principal Design Verification Engineer
Astera Labs
Salary undisclosed
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Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
We are seeking talented Design Verification Professionals with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage.
Responsibilities:
- Develop and execute block-level and system-level verification plans.
- Write and execute test sequences and collect and close coverage.
- Collaborate with RTL designers to debug failures and refine verification processes.
- Utilize coding and protocol expertise to contribute to functional verification.
- Develop user-controlled random constraints in transaction-based verification methodologies.
- Write assertions, cover properties, and analyze coverage data.
- Create VIP abstraction layers for sequences to simplify and scale verification deployments.
Basic Qualifications:
- Minimum of 12 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.
- Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred).
- Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance.
- Knowledge of industry-standard simulators, revision control systems, and regression systems.
- Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction.
Required Experience:
- Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.
- Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.
- Ability to independently develop test plans and sequences in UVM to generate stimuli.
- Experience writing assertions, cover properties, and analyzing coverage data.
- Developing VIP abstraction layers for sequences to simplify and scale verification deployments.
Preferred Experience:
- Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC.
- Experience with buffering and queuing with QoS on complex NOC-based SoCs.
- Analyzing performance at the system level on switching fabrics.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About this role
Astera Labs is building connectivity infrastructure for AI systems, and this role sits at the center of verifying the complex semiconductor designs that make that possible. As Principal Design Verification Engineer, you'll own functional verification across block and system levels for PCIe and CXL protocol implementations—the standards that underpin modern server and AI infrastructure. This means translating protocol specifications into verification plans, writing test sequences in UVM, developing verification IP abstraction layers, and collaborating closely with RTL designers to catch and resolve issues before silicon.
The position demands deep expertise: at least 12 years working on complex SoC or silicon products, strong grounding in electrical or computer engineering, and hands-on proficiency with PCIe/CXL Gen3+ verification, industry simulators, and coverage-driven methodologies. You'll need to work independently, interpret technical standards, and manage the full verification lifecycle from planning through coverage closure. Experience with physical and link layer protocol compliance, NOC-based systems, and performance analysis on switching fabrics would strengthen your candidacy.
This is an in-office role in Bengaluru suited to a senior verification engineer ready to take ownership of critical verification work on infrastructure that directly enables AI deployment at scale.
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