Lead DFT Engineer (Edge Computing)
EnCharge AI
Salary undisclosed
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Description
EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Job Description: Lead DFT Engineer (Edge Computing)
Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.
As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.
Key Responsibilities
Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.
Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.
Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.
Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.
Technical Requirements
Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role.
Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).
Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).
Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).
Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.
About this role
EnCharge AI is building next-generation in-memory computing hardware for edge AI applications, and this role sits at a critical juncture: ensuring their silicon is both manufacturable and reliable in the field. As Lead DFT Engineer, you would own the testing architecture for complex SoCs destined for power-constrained, remote environments—meaning your DFT strategy has to balance aggressive test coverage with minimal area and power overhead. You'd define hierarchical scan, compression, MBIST, and in-system test approaches from the ground up, then shepherd them through implementation, post-silicon validation on ATE, and yield optimization alongside design and physical teams.
This is a leadership position that demands both hands-on technical depth and architectural vision. You need 12+ years of DFT experience with at least two years leading or owning major initiatives, fluency with tools like TestMAX or Tessent, and proven expertise in memory BIST, advanced scan techniques (IJTAG, boundary scan), and low-power/multi-voltage design patterns. A track record on FinFET nodes (7nm and below) is essential. The role requires you to be equally comfortable defining strategy and debugging silicon failures on real hardware—this isn't a pure management track.
If you've spent your career solving DFT problems at leading-edge nodes and are energized by the intersection of reliability engineering and edge computing constraints, this is a hands-on technical leadership opportunity at a company with deep semiconductor pedigree.
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