Senior RTL Design Engineer
SambaNova Systems
$120,000 - $200,000 / year
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Description
SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.
About the team
The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with
About the role
SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture
Required Qualifications
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 5+ years of experience in ASIC RTL design
- Solid foundation in computer architecture and digital logic design
- Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
- Experience making design decisions that trade off power, performance, and area
- Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
- Experience with digital logic synthesis tools and static timing analysis
- Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
- Experience implementing SystemVerilog Assertions to check design intent
- Familiarity with tools and simulators for hardware performance analysis and tuning
- Familiarity with Git for managing release cycles
- Scripting skills in Python and Linux shell
Preferred Qualifications
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Exposure to a full ASIC development cycle through tape-out and production silicon
- Interest in or knowledge of AI workload acceleration techniques
- Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
- Exposure to emulation or FPGA prototyping platforms for pre-silicon validation
Base Salary Range:
Submission Guidelines
Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.
EEO Policy
SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.
Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.
Benefits
- health insurance
- stock options
About this role
SambaNova is building AI acceleration hardware, and this role puts you at the center of that effort. As a Senior RTL Design Engineer, you'll own specific blocks within the Reconfigurable Dataflow Unit (RDU) ASIC—designing the compute datapath, on-chip network, and memory subsystems that power the company's AI platform. You'll move your work from microarchitecture specification through RTL implementation, timing closure, and silicon bring-up, collaborating with architects, verification engineers, and physical design teams along the way.
The position demands deep ASIC expertise: at least five years of RTL design experience, strong SystemVerilog skills, and solid grounding in computer architecture and digital logic. You'll need hands-on familiarity with industry tools (synthesis, timing analysis, linting, CDC, LEC), standard protocols like AXI and PCIe, and memory interfaces such as HBM or DDR. Python and Linux scripting are expected, along with the ability to make informed trade-offs between power, performance, and area. Experience through a full tape-out cycle and knowledge of AI workload acceleration are preferred but not required.
This is an in-office role in Austin with a base salary of $120,000 to $200,000, plus equity and a comprehensive benefits package including strong medical coverage, wellness programs, and financial planning support.
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Pay for this role
$120,000 to $200,000 per year
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