Design Verification Engineer
SambaNova
$120,000 - $200,000 / year
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Description
SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.
About the team
The Design Verification team works on the RDU, SambaNova's chip for machine learning and AI workloads. This group focuses on chip-level control and initialization: sequencing, state transitions, clocking, and recovery across multiple subsystems on the chip. You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure. The team works closely with the broader verification organization, so debugging and root-causing issues often means coordinating across groups rather than working in isolation.
About the role
SambaNova Systems is looking for a talented and motivated Design Verification Engineer, DFT to help us build state of the art RDU chips for machine learning and artificial intelligence.
Responsibilities
- Develop and execute comprehensive verification plans for complex chip-level control and initialization features
- Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and functional coverage
- Verify complex sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems
- Develop directed and constrained-random tests to identify architectural and implementation corner cases
- Closely work with architects, RTL designers, firmware, and other verification teams to understand design intent and drive verification closure
- Debug simulation and regression failures and work with design teams to root-cause and resolve issues
- Analyze regression failures, functional and code coverage and drive verification to closure
Required Qualifications
- B.S. in Computer Science, Computer Engineering, or related field
- 5+ years relevant industry experience
- Strong understanding of digital design, SoC architecture, and verification methodologies
- Strong proficiency in SystemVerilog and UVM is required
- Experience with constrained-random verification, functional coverage, and assertion-based verification
- Good understanding of chip initialization, control sequencing, clocking, and cross-domain interactions
- Strong simulation debug and problem-solving skills
- Proficiency in scripting languages, e.g. Python, Perl, TCL and shell scripting, etc. is required
Preferred Qualifications
- Familiarity with CDC/RDC concepts and verification methodologies
- Fluency in Claude / AI tools for verification development and debug
Base Salary Range:
Submission Guidelines
Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.
EEO Policy
SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.
Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.
About this role
SambaNova's Design Verification Engineer role focuses on verifying the RDU chip's control and initialization logic—the sequencing, state transitions, clocking, and recovery mechanisms that coordinate across multiple subsystems. You'll develop SystemVerilog and UVM verification environments, write directed and constrained-random tests, and own verification plans from creation through closure. The work involves close collaboration with architects, RTL designers, and firmware engineers to understand design intent and debug failures when they occur.
This position requires at least five years of industry experience with strong fundamentals in digital design, SoC architecture, and verification methodologies. You'll need solid proficiency in SystemVerilog and UVM, hands-on experience with constrained-random verification and assertion-based techniques, and fluency in scripting languages like Python, Perl, or TCL. Familiarity with clock domain crossing and cross-domain interactions is important; experience with CDC/RDC verification is a plus.
The role is based in San Jose and requires in-office work. The salary range is $120,000 to $200,000, with benefits including 95% medical premium coverage for employees, dental and vision, disability insurance, and wellness programs like Headspace and Gympass+.
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Pay for this role
$120,000 to $200,000 per year
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