Principal Physical Design Engineer, Methodology
Astera Labs
$185,000 - $240,000 / year
Need a reasonable accommodation to apply or interview? Contact us.
JobMinglr uses automated technology to recommend jobs based on profile information and job preferences. Match Score does not determine eligibility for a position, prevent a user from viewing or applying to a job, or make hiring decisions on behalf of an employer.
Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
As a Principal Physical Design Engineer - Methodology, you will define, develop, and maintain the reusable physical design flows and automation infrastructure that the entire PD team relies on. You will build the RTL-to-GDSII flow, integrate and qualify tools from multiple vendors (Cadence and Synopsys), and continuously improve PPA and schedule predictability across all programs. You are the force multiplier scaling the team's capabilities and enabling faster, better tapeouts. This role is fully on-site at our San Jose, CA location.
Key Responsibilities:
- Flow & Methodology Ownership
- Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR
- Own the end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains (Cadence Innovus, Tempus, Voltus, Pegasus; Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC)
- Evaluate and qualify new tool features, foundry enablement kits, and flow enhancements to continuously improve PPA and schedule predictability
- Integrate and maintain DRC/LVS/extraction runsets and ensure consistency with foundry requirements
- Automation & Scale
- Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage
- Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across programs
- Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization
- Standards, Quality & Enablement
- Establish best practices, runset standards, and quality checks that scale across multiple concurrent tapeout programs
- Support physical design engineers with flow issues, tool configurations, and methodology guidance
- Drive adoption of flow improvements across the team, including training and documentation
Basic Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Masters Preferred.
- 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below)
- Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows
- Experience with both Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains
- Expert-level scripting ability in Python, Tcl, and/or Perl for flow development and automation
- Experience building and maintaining multi-corner/multi-mode analysis infrastructure
- Understanding of foundry design rules, technology files, and enablement kit integration
- Ability to work independently with strong prioritization and a results-driven mindset
Preferred Qualifications:
- Knowledge of agentic AI solutions for EDA automation
- Experience with CI/CD integration for physical design flows
- Familiarity with compute farm management and job scheduling optimization
- Knowledge of advanced packaging or multi-die integration flows
The base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Benefits
- bonus
About this role
Astera Labs is seeking a Principal Physical Design Engineer to own the methodology and automation infrastructure that powers the company's entire physical design organization. In this role, you'll architect and maintain the RTL-to-GDSII flow across multiple vendor toolchains (Cadence and Synopsys), qualify new tools and foundry enablement kits, and continuously optimize for power, performance, area, and schedule predictability. You'll be the force multiplier enabling faster, higher-quality tapeouts across concurrent programs.
The position demands deep expertise in advanced-node physical design flows—synthesis, place-and-route, extraction, STA, and EMIR—combined with expert-level scripting in Python, Tcl, and Perl to build scalable automation infrastructure. You'll need 8+ years of hands-on experience with both Cadence and Synopsys toolchains on complex SoCs at 7nm and below, plus the ability to integrate DRC/LVS runsets, manage multi-corner analysis at scale, and work effectively with foundry design rules and technology files. This is an independent contributor role requiring strong prioritization and results-driven execution.
The role is fully on-site in San Jose and offers a base salary of $185,000 to $240,000 depending on experience. If you have additional experience with AI-driven EDA automation, CI/CD integration for design flows, or advanced packaging and multi-die integration, those would strengthen your candidacy.
How this employer is doing
average
- H1B: Sponsors Visas
- Sponsors Visas
This role's local market on JobMinglr
Pay for this role
$185,000 to $240,000 per year
That is the employer's posted range, and where you land in it is usually decided in one conversation. Before that conversation, run the numbers: analyze an offer for this role.
Before you apply, worth reading
How JobMinglr reads this job
Every listing here is scored against your profile before you apply: skills overlap, experience level, location and work arrangement, each weighted and explained. You see the score and the reasons, not just a list. How the matching works.