Firmware Engineer Tech Lead
Astera Labs
$160,000 - $200,000 / year
Need a reasonable accommodation to apply or interview? Contact us.
JobMinglr uses automated technology to recommend jobs based on profile information and job preferences. Match Score does not determine eligibility for a position, prevent a user from viewing or applying to a job, or make hiring decisions on behalf of an employer.
Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. As a Firmware Engineer Tech Lead you are responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended.
Basic Qualifications
- Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
- Minimum 5 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC).
- Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately.
Required Experience
- Experience working on PCIe-Express (Gen-3 and above) protocol, including working with analyzers and exercisers to debug protocol issues.
- High level of proficiency in C (preferred) or C++, including development of C-based SDKs.
- High level of proficiency in Python for automating pre-processors/post-processors and FW QC.
- Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub.
- Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, DDR Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces.
Preferred Experience
- Experience with PAM4 SerDes with working knowledge of Tx/Rx equalization, adaptation, CDR and SerDes link budgets.
- Hands-on experience with PCIe devices in Server, Storage, and/or Networking equipment.
- Experience developing embedded firmware for PCIe or Ethernet Switch products.
Base salary range is $160,000 to $200,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Benefits
- bonus
About this role
Astera Labs is seeking a Firmware Engineer Tech Lead to architect and develop firmware and microcontroller subsystems for its AI infrastructure connectivity products. This role sits at the intersection of hardware and software, with firmware treated as a core differentiator rather than an afterthought—you'll work closely with logic designers to implement major product features and often engage directly with customers to ensure their needs are met. The position requires deep expertise in PCIe protocol (Gen-3 and above), strong C or C++ proficiency, and hands-on experience debugging complex SoC interfaces across server, storage, and networking applications.
You'll need at least five years developing firmware for sophisticated silicon products, with demonstrated ability to work on-chip microcontrollers and system management controllers. Proficiency in Python for test automation, familiarity with build tools like gcc and Make, and knowledge of common SoC IP blocks (PCIe, DDR, NVMe controllers, AMBA/AHB interfaces) are essential. Experience with PAM4 SerDes, embedded PCIe or Ethernet switch development, and hands-on work with PCIe devices in production environments would strengthen your candidacy.
This is a full-time, in-office role in San Jose with a salary range of $160,000 to $200,000, plus discretionary bonus and benefits. You'll need a Bachelor's degree in electrical engineering or computer science (Master's preferred), authorization to work in the US, and the ability to manage competing priorities with minimal supervision while maintaining a customer-focused mindset.
How this employer is doing
average
- H1B: Sponsors Visas
- Sponsors Visas
This role's local market on JobMinglr
Pay for this role
$160,000 to $200,000 per year
That is the employer's posted range, and where you land in it is usually decided in one conversation. Before that conversation, run the numbers: analyze an offer for this role.
Before you apply, worth reading
How JobMinglr reads this job
Every listing here is scored against your profile before you apply: skills overlap, experience level, location and work arrangement, each weighted and explained. You see the score and the reasons, not just a list. How the matching works.