EDA Engineer (RFIC Engineering)

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. EDA ENGINEER (RFIC ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system.

Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, hands-on, proactive, and intellectually curious EDA Engineer to help support and improve the IC design environment used by silicon design, layout, verification, physical design, and methodology teams. The role focuses on keeping EDA tools reliable, PDK and flow usage reproducible, and designers productive across analog/RF/mixed-signal and digital silicon workflows. This is a growth-oriented role for an engineer with strong fundamentals in electrical engineering, computer engineering, computer science, Linux, scripting, or IC design tools.

The engineer will partner design teams, other EDA engineers, IT/server teams, foundries, and EDA vendors to triage production issues, improve tool flows, build lightweight automation, maintain documentation, and convert repeated support issues into reusable methodology.

RESPONSIBILITIES

: Support day-to-day EDA/CAD workflows for RFIC and silicon engineering teams, including tool launch, environment setup, PDK usage, simulation, physical verification, extraction, and related Linux workflows Support analog/RF/mixed-signal specific flows (Virtuoso, Spectre, EM tools, etc.) in addition to digital and physical verification flows Assist with PDK installation, qualification, version tracking, release notes, and deployment support for supported foundry processes Triage DRC, LVS, PEX, simulation, EM, license, HPC, and environment issues using reproducible debug practices: command, log path, tool version, PDK version, run directory, expected result, actual result, and reproduce status Maintain and improve tool launch wrappers, setup scripts, environment modules, path configuration, project templates, and onboarding material Build lightweight automation in Python, Tcl, SKILL, shell, Perl, Makefile, or similar languages for log collection, preflight checks, license/tool health checks, regression reporting, and recurring issue reduction Create and run targeted QA tests for PDK updates, tool upgrades, wrapper changes, vendor patches, and flow changes before broad deployment Maintain clear runbooks and Confluence documentation for common EDA flows, including DRC/LVS/PEX debug, Cadence/Virtuoso setup, simulation setup, HPC job submission, license issues, and common user errors Partner with design, layout, verification, physical design, IT/HPC, foundry, and EDA vendor teams to resolve blocked flows and improve methodology robustness Identify recurring support patterns and help convert one-off fixes into durable flow changes, documentation, automation, or vendor/IT escalations Support configuration-management and data-management workflows, such as Perforce, Cliosoft, or similar systems, as needed for silicon design teams Contribute to modern EDA workflow improvements, including AI-assisted log triage, rule-deck validation, issue classification, signoff reporting, and designer self-service tools under senior guidance BASIC

QUALIFICATIONS

: Bachelor's degree in electrical engineering, computer engin