Distinguished Engineer, ASIC (CONTRACT)

Company Description Butterfly Network, Inc. (NYSE: BFLY) is driving a digital revolution in ultrasound imaging and sensing with its proprietary Ultrasound-on-Chip™ semiconductor technology and software solutions. Butterfly first proved its technology in the point-of-care ultrasound market – commercializing the world’s first single-probe, whole-body portable ultrasound device, which is now on its best-selling, third-generation: Butterfly iQ3™.

The Company combines its advanced hardware with cloud software and AI, an enterprise workflow solution (Compass AI™) and other offerings to drive adoption of affordable, accessible ultrasound. Butterfly also enables third-party development of imaging AI apps through Butterfly Garden™, its software development kit and AI partnership initiative. In addition to its medical imaging products, Butterfly Embedded™ is the Company’s Ultrasound-on-Chip™ licensing and co-development program designed to enable a new wave of ultrasound-enabled technologies across non-competitive healthcare markets and beyond.

Through Butterfly Embedded™, partners can build and scale novel ultrasound applications powered by Butterfly’s proprietary semiconductor chip and software platform. Butterfly’s innovations have been recognized by Prix Galien USA, Fierce 50, TIME’s Best Inventions and Fast Company’s World Changing Ideas, among other achievements. We’re a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging.

Let’s build something extraordinary together! Job Description The role of the Distinguished Engineer, Digital ASIC Designer offers the opportunity to work within the heart of the product development team to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products.

Qualifications

Baseline skills/experiences/attributes: BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience. 8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership. Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs.

Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design. Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces. Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design.

Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP. Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff.

Requirements

and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts). , DSP, beamforming, AI, or MAC-heavy/vector datapaths). Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures.

, AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs.