Senior, CPU Architecture & Performance Research Engineer

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’Ll Do

Architecture Research Lab is seeking Senior CPU Architecture Performance Engineer to contribute to performance analysis and microarchitectural optimization of current and next-generation CPU (RISC-V) cores. This role emphasizes hands-on analysis, modeling, and close collaboration with architects and design teams to improve performance across real-world workloads. You will focus on executing well-defined performance studies, identifying bottlenecks, and helping translate architectural ideas into measurable performance gains Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy Job ID: 42851 Perform performance analysis for CPU microarchitectural features under guidance from Staff and Principal engineers.

Run architectural simulations and analyze results (IPC, CPI stacks, latency and throughput metrics). Identify performance bottlenecks in frontend, execution engine, or memory subsystems. Assist in evaluating design trade-offs using trace-driven or cycle-accurate models.

Characterize workloads and benchmarks (SPEC, server, client, internal traces). Develop scripts and tools to automate performance analysis. Work leading to patents and publication.

What You Bring Master’s, or PhD in Computer Engineering, Computer Science, or related field. 2+ years of experience in CPU microarchitecture and/or performance engineering. Strong understanding of: Out-of-order execution, branch prediction, pipelines, and speculation Cache coherence, memory systems, prefetching, and NUMA effects Hands-on experience with architectural simulators (like gem5).

Strong programming skills in C/C++ and Python. Experience analyzing large performance datasets and traces. Familiarity with compiler optimizations and hardware/software co-design.

Preferred Qualifications

Experience with RISC-V, ARM or X86 architectures. Background in power/performance/area (PPA) trade-off analysis. Familiarity with SIMD / Vectors / VME for AI inference workloads.

Prior tapeout / patent / publication experience. You’re inclusive, adapting your style to the situation and diverse global norms of our people. You approach challenges with curiosity and resilience, seeking data to help build understanding.

You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change.

What We Offer

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.

Benefits

centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.