Principal Engineer, SOC Design

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’Ll Do

The DRAM Development Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash. DDL’s vision is to solve key problems of Cloud Data center by developing the new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions.

We are an integral part of Samsung’s strong R D focus lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps. Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing.

You’ll focus on enhancement of memory and storage capability by developing prototype and production controllers. Job ID: 42866 Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level. Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).

Reviews 3 rd party IPs including ARM cores, DDR controller, and UCIe PHY Responsible for integrating the third part IPs and sub system at top level Work closely with architects and verification engineers to ensure sound design at SoC level. Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis What You Bring Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred. Highly motivated with good verbal and written communication skills.

Hands on knowledge experience in ASIC design flow from design to tape out. Experience Good knowledge in ATE vector generation, testing and silicon bring up. Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.

Good understanding of PPA (performance, power, and area) trade-offs. Experience in SoC level synthesis, timing analysis, lint check, CDC checks. Experience in interfacing 3 rd party service companies for DFT/PI/PD.

Good knowledge and experience in AMBA bus fabric, ARM cores. Self-motivated problem-solver with an ability to work well in a team. You’re inclusive, adapting your style to the situation and diverse global norms of our people.

An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change.

What We Offer

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience.