Senior Hardware Validation & SI Correlation Engineer

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale. SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations.

Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.

About The Role

SambaNova Systems is redefining what’s possible in AI infrastructure—and the hardware that powers it has to be flawless. As a Senior Hardware Validation SI Correlation Engineer, you will own the technical bridge between simulation and silicon, ensuring that every high-speed link, control bus, and power rail in our next-generation AI server systems performs without compromise. This is a high-impact, highly visible role that blends deep Signal Integrity (SI) expertise with rigorous system-level hardware validation.

You will work at the frontier of AI compute—validating PCIe Gen5/6, DDR5, and 112G/224G Ethernet interfaces on systems pushing the limits of what data center hardware can do. If you thrive in a fast-paced lab environment, love digging into root cause, and want your work to directly accelerate the future of AI, this role is built for you.

What You’Ll Do

SI Modeling Measurement Correlation Drive the correlation between pre- and post-layout SI simulations and physical lab measurements, closing the loop between theory and hardware reality. Quantify simulation-vs-measurement gaps for PCIe Gen5/6, DDR5, and 112G/224G Ethernet using S-parameters, TDR, and eye diagram analysis. Develop and refine EM models for PCB discontinuities, high-speed connectors, and vias using Ansys HFSS, Cadence Sigrity, or equivalent tools.

Investigate discrepancies caused by manufacturing tolerances, material properties (Dk/Df), or de-embedding inaccuracies and drive them to resolution. System-Level Electrical Validation Lead validation of housekeeping and control buses—I2C, SPI, eSPI, UART, SMBus—ensuring protocol compliance and robust timing margins. Validate complex power-on/off sequences and correlate VR control loop simulations with physical transient response and ripple measurements.

Ensure reliable operation of sideband signals, reset logic, and BMC hardware interfaces under intensive AI workloads. Work cross-functionally with SI, Power Integrity (PI), and Firmware teams to resolve system-hang and link-training failures rooted in electrical noise or power instability. Test Methodology Automation Author comprehensive Hardware Validation Plans (HVP) with full coverage of critical electrical test points.

Build Python-based automation scripts to drive data collection from VNAs, BERTs, and oscilloscopes—accelerating validation throughput and repeatability. S. S.

S. preferred). 10+ years of experience in high-speed digital design or hardware validation within a data center, systems architecture, or server bring-up environment.

Expert-level proficiency in SI/EM tools: Ansys HFSS/SIwave, Cadence Sigrity/Allegro, or Keysight ADS. Hands-on mastery of high-bandwidth real-time oscilloscopes, VNAs, and logic analyzers. 3) and low-speed control buses (I2C, SPI).

Strong fundamentals in digital circuit design, debug, and computer architecture. Familiarity with the unique power and thermal challenges of high-density AI clusters—including 48V power delivery and high di/dt transients.