K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization.

If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a Senior Mixed-Signal Verification Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space.

Your work will directly influence top-level integration and silicon tapeout success. This is a high-impact, technical role with significant ownership across modeling, methodology, verification, and cross-functional alignment with RF, analog, and digital teams.

Responsibilities

). Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog. Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog).

Integrate AMS models into digital verification environments (UVM-based). Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification. Support architectural exploration through early-phase modeling and system-level simulations.

Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions. Work with digital and verification teams to ensure seamless integration of AMS models. Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up.

Act as technical leader and subject-matter expert.

Required Qualifications

S. D. in Electrical Engineering, Computer Engineering, or related field.

5+ years of experience in analog/mixed-signal modeling and/or AMS verification. Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages. Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers).

Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar).

Preferred Qualifications

Experience building AMS verification methodologies from scratch. Familiarity with UVM-based verification and digital design flows. Knowledge of signal processing theory, RF system modeling, or communication systems.

Experience with MATLAB/Simulink, Python modeling, or SystemC AMS for high-level architectural modeling. Experience working in cross-functional, geographically distributed teams.

Compensation

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Benefits

: Base salary range for this role is $160,000 – $230,000 + equity in the company Salary will be based on several factors includ