Micro-Architect and RTL Designer

What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI.

Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.

What You'Ll Do

Here Contribute to MatX’s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results

Who You Are

Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon 4 years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals Hands-on experience with design synthesis, design lint, and related flows to take designs to high quality sign-off Familiarity with verification, emulation platforms and methodologies is a plus Experience with high speed I/O IP is a plus A lot of experience with logic that focuses on moving, storing, or managing data such as caches, buffers, crossbars, etc… is a plus This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday

Compensation

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training.

. Early Career - $120,000 - $275,000 + equity Mid Career - $175,000 - $450,000 + equity Senior Career - $275,000 - $600,000 + equity

What We Offer

g. conferences, courses, and other learning opportunities Team Connection Team Lunches, quarterly off-sites, and regular town halls Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don’t! Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses Commute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!

Perks

you care about most Remote

We work remotely Monday Friday, supported by