About The Role

We are seeking a Senior DVT Engineer with deep expertise in High-Speed SerDes and Line-Side Electrical Characterization to join our Optical DSP division. This role is a critical technical juncture, ensuring the electrical integrity of our Coherent ASICs from the Host-side (Client) interfaces to the Line-side (Optical Interface) analog data paths. The successful candidate will lead the validation of the industry’s most advanced 112G/224G interfaces, providing the foundational stability required for multi-terabit coherent transmission.

You will be responsible for defining test strategies, executing complex silicon characterization, and debugging the interface between high-speed electrical signals and the DSP's digital core.

What You Will Do

: Host-Side SerDes Validation: Lead the post-silicon characterization of multi-lane SerDes (112G/224G) across full PVT corners, focusing on Bit Error Rate (BER), jitter tolerance, and adaptive equalization (CTLE, DFE). Line-Side Electrical Characterization: Validate the high-speed analog interface between the DSP and the Optical Front End (OFE). Characterize DAC-to-Modulator and TIA-to-ADC paths for bandwidth, frequency response flatness, and total harmonic distortion (THD).

Signal Integrity Impairment Analysis: Quantify and mitigate electrical impairments including I/Q Skew, I/Q Gain Imbalance, and Phase Noise at the package and ball level. 3 standards, while maintaining adherence to internal high-performance specifications for line-side linearity. , reflections, crosstalk, or power supply noise) impact optical constellation quality and Error Vector Magnitude (EVM).

Automation Development: Architect Python-based automation frameworks for complex "sweep" testing, including S-parameter extraction and VSR/XSR link margin analysis.

Requirements

Host-Side SerDes Modulation Signaling Mastery: Expert knowledge of PAM4 signaling, including Gray mapping and MSB/LSB error distribution. Equalization: Deep proficiency in optimizing adaptive filtering (FFE, CTLE, and DFE) and understanding their impact on Signal-to-Noise Ratio (SNR). , PAM6, PAM8) or experimental signaling schemes for 224G+ architectures is highly preferred.

Jitter Analysis: Expert-level ability to decompose jitter (RJ, DJ, BUJ) and analyze bathtub curves. Line-Side High-Speed Analog Converter Metrics: Experience validating high-speed ADC/DAC performance, including effective number of bits (ENOB), SFDR, and sampling jitter. Frequency Domain Analysis: Mastery of $S$-parameter analysis ($S_{11}, S_{21}, S_{22}$) and TDR for identifying impedance mismatches in the DSP-to-Package-to-Module transition.

Line-Side Linearity: Ability to measure and optimize the linearity of the high-speed transmit path to minimize penalties in high-order QAM optical modulation. Instrumentation Tools Laboratory Hardware: Expert operation of 110GHz+ Real-time/Sampling Oscilloscopes , Bit Error Rate Testers (BERTs), Vector Network Analyzers (VNAs), and High-Speed AWGs. Software/Scripting: Advanced Python skills (NumPy, Pandas, PyVISA) for automated instrument control and large-scale data analytics.

What you Will Bring: Education: Bachelor’s or Master’s Degree in Electrical Engineering (PhD focused on High-Speed I/O or Mixed-Signal design is a plus). Experience: 5+ years in high-speed hardware validation or DVT, with a specific focus on Coherent Optical or high-performance networking ASICs. , bandwidth limitations or non-linearity) translates to optical metrics such as OSNR penalty.