SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR.

SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together.

We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe.

These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES

QUALIFICATIONS

: Bachelor’s degree in electrical engineering, computer engineering or computer science 5+ years of ASIC and/or physical design flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms Knowledge of deep sub-micron FinFET and CMOS solid state physics Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic Familiar with CMOS analog circuit and physical design Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.) Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment ADDITIONAL

REQUIREMENTS

: Ability to work extended hours and weekends as needed to meet critical project milestones ITAR

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Department of State. Learn more about the ITAR here .

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)