Physical Design - CAD Lead

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years.

Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution Efficient is seeking a CAD Lead - PD flows/infrastructure to join our growing team. The ideal CAD Lead would have worked on significant portion of the full gamut of Physical Design flows and flow infrastructure (flowtracer etc). This role is in a newly formed hardware engineering group and is the seed hire for this discipline.

You will get to setup CAD flows and infra from scratch and influence and shape this aspect in the future. This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

Drive and develop PD flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime. Help develop repeatable, predictable , design and process agnostic PD flows. Develop state of the art flow infrastructure to enable consistent and rapid design under tight schedule constraints for multiple product lines in the energy efficient edge AI computing market.

Work closely with PD team leads to propose and develop end to end build and signoff flows. Build regression frameworks for ensuring high quality flows and achieve hardware engineering vision of spending 90% or more time on actual design tasks and NOT wrestling with tools. Develop collateral quality checking utils to ensure high design efficiency.

Develop and deploy a unified environment for specifying all collaterals (stdcell, memory, PDK, hardips…) and all flow dependencies (cycle time, PVTRC corners, per flow design and process dependent configuration). Work with 3rd party vendor resources and coordinate their work. Continuously work on improving flow consistency and efficiency in the context of multiple product lines.

Required Qualifications

Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience Strong python other scripting programming skills. ) Intimate knowledge of hardware design workflows for Physical Design and RTL/DV. Excellent scripting skills in TCL, shell and python.

Qualifications

Experience

Requirements

Experience in full chip RTL/DV and PD flows. Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers. Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.

Experience in integrating analog or mixed-signal macro on top-level design. Experience in verifying IP collaterals.

Benefits

. The final

Compensation

package will be based on your experience and location, with some flexibility to en