Senior FPGA Developer (SystemVerilog)

The Role The Senior FPGA Developer will be a member of the core team building the Quantum Key Distribution system. The focus is end ‑ to ‑ end RTL ownership on AMD/Xilinx (Artix ‑ 7, Kintex UltraScale): architect, implement, verify, and close timing on high ‑ rate interfaces and deterministic pipelines. The role also sets engineering discipline for FPGA development and mentors a junior engineer.

The Senior FPGA Developer owns the FPGA architecture/codebase and collaborates closely with embedded/software to define clean contracts, ensure reliable bring ‑ up, and deliver reproducible, versioned bitstreams.

Responsibilities

The Senior FPGA Developer should expect to work in the following activities.

Requirements

The Senior FPGA Developer is expected to have the following

; eligibility is determined by the competent authorities.

Qualifications

and experience. 5+ years production FPGA on AMD/Xilinx; expert SystemVerilog RTL Demonstrated mentoring of junior engineers Strong constraints/timing (XDC), CDC/reset, and practical floorplanning; consistent timing closure Hands ‑ on DDR3/DDR4, PCIe endpoints/DMA, Ethernet/SFP; integrating/evaluating third ‑ party MAC/PCS IP Strong verification background; experience with self-checking testbenches and regression testing, proficiency with ModelSim/Questa. Knowledge of OSVVM/UVM is a plus CI for HDL: scripted sim/synth/impl (Tcl/Make/Python), lint, artifact/version management; board bring ‑ up and ILA ‑ based debug System integration with SW/FW: register maps, driver contracts, HIL Proficiency in written and spoken English Ability to be on-site in Munich or Potsdam offices to work with hardware, when required Applicants must have the right to work in Germany at the time of application.

We do not provide visa sponsorship. S. Secret (or higher) security clearance or (b) an EU SECRET (or national equivalent) personnel security clearance.