Physical Design Engineer, PnR

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.

We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC.

You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II. Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability. g.

I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST). What we need Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC. Help close EM/IR, ensure UPF power intent is consistent with implementation, and drive LEC and physical verification signoff for your partitions in coordination with methodology owners.

Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. What you will learn How to implement and close AI SoC partitions end-to-end, including power intent, timing, and physical signoff in a modern Synopsys-based flow. Deeper expertise across signoff domains: EM/IR, DRC/LVS, logical equivalence (LEC/Formality), and CDC-aware implementation on meaningful production blocks.

Practical integration of analog/mixed-signal macros (PLL/DLL), DFT features (OCC/MBIST), and SoC interface IP within advanced physical design flows and collaborative tapeout environments.

Compensation

for all engineers at Tenstorrent ranges from $100k - $500k including base and variable

targets. Experience, skills, education, background and location all impact the actual offer made.

package and

Benefits

, and we are an equal opportunity employer. S. S.

EAR Country Groups D:1, E1, or E2 country. S. export-controlled technology.

S. S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).

Requirements

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