ASIC Verification Engineer

About Tensordyne AI is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different modalities and environments - with the ability to quickly learn and then solve complex problems. Tensordyne is an AI system solution company that builds very high-performance, low-power generative AI inference systems.

Our mission, through the creation of custom silicon, hardware and software, is to enable multimodal Generative AI inference acceleration at scale, with safe, sustainable, high-performance systems for our hyperscaler and neocloud data center customers. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely across North America and Europe.

Benefits

, competitive

Compensation

, flexible spending options, and recognition programs, because building category-defining technology starts with a healthy, supported team. Come join us as we shape the future of multimodal generative artificial intelligence!

About The Role

: As a member of Tensordyne's ASIC team, you will be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company’s flagship perception module product for autonomous driving applications. This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record- breaking computational performance at low power.

Responsibilities

: Your

will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular System Verilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks. SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation) Develop the block-level, sub-system and full-chip verification environment and tests to implement test plans.

Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances. Triage and debug functional and performance issues with the design-under-test. Handle bug tracking and coverage convergence.

Perform diagnostic and post-silicon validation tests in the lab.

Required Qualifications

: 2+ years of ASIC verification experience. Knowledge of ARM/MIPS/RISC-V Architecture Familiarity with AMBA/APB/AXI Protocol Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C .... Excellent Verilog/System Verilog programming skills.

Experience with UVM (or similar). Deep understanding of object oriented programming principles, constrained random stimulus, and a coverage driven verification approach. Scripting experience (Python, Perl, TCL, shell programming) highly-desirable.

Interest to explore AI architectures for convolution, transformer and other kinds of workloads Self-starter and highly-motivated to work in a dynamic start-up environment. S. S.

preferred) degree in Electrical or Computer engineering (or similar field).