Senior ASIC Design Verification Engineer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization.

If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply. The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.

This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.

Responsibilities

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models. Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.

Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios. Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues. Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.

Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations. Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices. Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.

Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis. Participate in ASIC team interviews. Contribute to advancement of DV methodologies and improvements.

Engage external IP providers and verification partners when needed.

Qualifications

S. S. in Electrical Engineering, Computer Engineering, or related field.

5+ years of experience in ASIC/SoC verification. Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows. Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).

Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions. Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation. Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).

Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).

Nice To Have

Experience with developing and integrating reference models.