Principal FPGA / RTL Design Engineer - Signal Processing

THE COMPANY Silvus Technologies , a leading provider of advanced MANET and MIMO communications systems, is reshaping mesh network technology for mission-critical applications – on the ground, in the air and at sea. Its battle-proven StreamCaster family of MANET radios and proprietary MN-MIMO waveform provides the vital communications link for defense, law enforcement and public safety agencies around the world, and in the toughest operational environments. With deep roots in DARPA research, Silvus Technologies develops world-class advanced communications technologies that are reshaping the tactical communications landscape.

From pure line-of-sight to extreme non-line-of-sight, Silvus radios form a self-healing, self-forming mesh network, enabling secure and reliable connectivity, including video and high-bandwidth data. Silvus Technologies is a wholly owned subsidiary of Motorola Solutions, Inc. Would you like to join an incredibly talented group of people, doing very challenging work, with the prime directive of “ Keeping Our Heroes Connected ”?

THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who will report to the Senior Engineering Director in Irvine and work closely with the FPGA Engineering team . The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products.

In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R D. These are exciting projects aimed at addressing challenging real-world communication needs. This Principal FPGA / RTL Design Engineer is 100% onsite, Monday through Friday, at Silvus Technologies’ Engineering and R D Office in Irvine, CA , near the vibrant Irvine Spectrum.

The following is a list of at least some of the current essential job functions of the position.

Responsibilities

at any time at its discretion.

Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks. RTL coding, simulation, and test bench development. FPGA synthesis and timing closure.

Hardware verification and troubleshooting; familiarity with logic analyzers. Provide support to the RF and Software Engineering teams.

REQUIRED QUALIFICATIONS

Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields. Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; 8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields. Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs.

Deep knowledge of RTL design fundamentals using Verilog and System-Verilog. Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs. S.

S. government contracts . All employment is contingent upon the successful clearance of a background check and drug testing..

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES MS. D. degree in Electrical Engineering, Computer Science, or relevant fields.

Basic MATLAB skills. Solid knowledge and understanding of scripting languages such as Perl and Python. Strong communication and presentation skills.

Experience with wireless communication systems on FPGA or ASIC designs.

REQUIREMENTS

Office environment. Occasional exposure to heat, cold, and allergens while performing tests or demonstrations in the field.