Platform Technical Project Manager, Rack-Scale AI Sysytems

What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI.

Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.

About The Role

MatX is building next-generation AI infrastructure systems for high-performance datacenter workloads. We are looking for a Senior Platform TPM, Rack-Scale AI Systems to drive design-phase execution for our rack-scale platform. This role will coordinate cross-functional execution across rack architecture, accelerator board design, power delivery, thermal and liquid cooling, high-speed interconnect, firmware, diagnostics, test vehicles, system validation, and external CM/JDM partner engagement.

You will work closely with Systems Engineering, hardware engineering, firmware, validation, supply chain, and external CM/JDM partners.

What You'Ll Do

Here Drive the integrated execution plan for rack and board design from architecture through design release. Own and maintain the design-phase master schedule across rack, board, power, thermal, interconnect, mechanical, firmware, diagnostics, validation, and supply-chain dependencies. Coordinate execution across key platform workstreams, including board electrical/SI/PI readiness, rack power, liquid cooling, cable/optical interconnect, BMC/telemetry, diagnostics, test vehicles, PLM/BOM/ECO readiness, and external CM/JDM design reviews.

Partner with Systems Engineering to define design gates, risks, dependencies, decision points, and exit criteria. Track critical path items, schedule risks, owners, closure dates, and escalation paths. Coordinate design-readiness reviews, DFX reviews, and implementation-readiness reviews with internal teams and external CM/JDM partners.

Drive readiness for system validation using test vehicles, including power, thermal, connectivity, diagnostics, instrumentation, telemetry, and validation planning. Maintain a live risk register covering design readiness, system validation readiness, power/thermal risks, interconnect risks, long-lead dependencies, and supply-chain risks. Ensure long-lead design dependencies are visible to supply chain, materials, and sourcing teams.

Prepare executive-level updates covering milestone health, top risks, decisions needed, critical path, and resource gaps. Ensure validation learnings are captured, tracked, and incorporated into the platform execution plan.

Who You Are

8+ years of technical program management, hardware engineering program management, systems engineering, or hardware platform development experience. Experience managing complex hardware platforms through architecture, design, validation, and design release. Experience working across electrical, mechanical, thermal, firmware, validation, manufacturing, supply-chain, and external partner teams.

Ability to drive schedules, dependency management, issue tracking, risk management, milestone governance, and executive-level communication. Experience coordinating design reviews and driving closure across cross-functional engineering teams. Working familiarity with several of the following areas: board design, power delivery, SI/PI, thermal design, liquid cooling, high-speed interconnect, firmware, diagnostics, rack integration, or system validation.

Experience working with ODMs, JDMs, contract manufacturers, or external engineering/manufacturing partners. Strong written and verbal communication skills, including the ability to summarize technical risks, tradeoffs, decisions, and schedule impact.